1. Field of the Invention
The present invention relates to semiconductor integrated circuit, and more particularly, to a bonding option circuit in a semiconductor integrated circuit.
2. Background of the Related Art
In a semiconductor integrated circuit, circuits having a variety of options for ease of design and test are established on a semiconductor chip to select a required circuit by inputting an external condition therein. For instance, when a semiconductor memory is designed to have one of various input/output structures such as xc3x974, xc3x978, xc3x9716 and the like, all the input/output structures of xc3x974, xc3x978, xc3x9716 are embodied on a single chip so that one of the structures should be selected in accordance with external conditions. The selective condition inputted from outside to select the single I/O structure. In general, a pad is formed for the selection of the corresponding I/O structure outside the chip, and a signal is applied to the pad.
A pad is for wiring between a chip and a lead frame. The pad is formed on the chip and supplied with a signal of external supply voltage level.
Thus, a buffer is required for transforming the signal applied to the pad into a logic signal of a internal voltage level of the chip. When there are many structures available for selection, one of the structures is selected by supplying selective conditions through at least two pads, and then, the selective conditions are decoded. This kind of circuit is called a bonding option circuit. Such a related art bonding option circuit is shown in FIG. 1 and FIG. 2.
FIG. 1 shows a block diagram of a bonding option circuit according to a related art. As shown in FIG. 1, the bonding option circuit of the related art has a pair of pads 102 and 108 to transmit selection conditions, a pair of buffers 104 and 110 to transform signals of the selection conditions into logic signals of an internal voltage level of a chip, and a decoder 106 to decode the logic signals and select one of the three I/O structures of xc3x974, xc3x978 and xc3x9716 in accordance with a combination of the logic signals.
FIG. 2 is a circuit diagram that shows a related art bonding option circuit, which is disclosed in U.S. Pat. No. 5,682,105 (BONDING OPTION CIRCUIT HAVING NO PASS-THROUGH CIRCUIT, 1997.10.28). As shown in FIG. 2 and the abstract of U.S. Pat. No. 5,682,105, a related art bonding option circuit has of a logic gate circuit 2 connected between a bonding pad 1 and a power supply voltage VDD, a load capacitance 4 connected between a ground and the logic gate circuit 2, and an output stabilizing circuit 3 having an input connected to the bonding pad 1 and an output connected to an output terminal OUT. When the bonding pad 1 is floated, the logic gate circuit 2 connects the bonding pad 1 to the power supply voltage VDD. When the bonding pad 1 is grounded, the logic gate circuit 2 cuts off a current path between the bonding pad 1 and the power supply voltage VDD. An objective of the bonding option circuit shown in FIG. 2 is to reduce leakage current generated when the bonding pad 1 is connected to the ground.
As described above, the related art bonding option circuit has various disadvantages. In an aspect of a semiconductor integrated circuit package, an area occupied by a bonding pad is relatively larger than that occupied by a chip. Thus, to reduce the size of the package, reducing the number of bonding pads is preferred to reducing the size of the chip. However, the bonding option circuit according to the related art should require a pad per selective condition. When the selectable structures are more than three, the number of the bonding pads and the buffers are increased also.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a multi-level buffer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a bonding pad circuit having a multi-level buffer that reduces a number of bonding pads and buffers.
Another object of the present invention is to provide a bonding pad circuit having a multi-level buffer that generates a plurality of selection signals from a single selection condition applied to a bonding pad.
Another object of the present invention is to provide a multi-level buffer generating a plurality of selection signals from a single selective condition applied to a bonding pad in order to reduce the number of the bonding pads and the buffers.
To achieve at least these and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a multi-level buffer according to the present invention includes a first current control circuit, a resistor, a second current control circuit, and a logic signal generator. The first current control circuit is coupled between a first node coupled to a pad and a power supply voltage and has a first current when a power-up signal is not activated and a second current that is larger than the first current when the power-up signal is activated. The resistor is coupled between the first node and a second node so that a voltage difference is generated between the first and second nodes. The second current control circuit is coupled between the second node and a ground and has a third current that is equal to the first current when the power-up signal is not activated and a fourth current that is equal to the second current when the power-up signal is activated. The logic signal generator generates a first buffer output signal and a second buffer output signal, respectively, by transforming signals of the first and second nodes into logic signals of an internal voltage level of a chip.
To further achieve the above objects in a whole or in part, and in accordance with the present invention, a multi-level buffer is provided that includes a variable voltage divider, a comparator circuit, and a logic signal generator. The variable voltage divider generates a first voltage, a second voltage, and a third voltage each having prescribed voltage levels that change in accordance with conditions applied to a pad where the variable voltage divider is activated by a power-up signal. The comparator circuit generates a first comparison result and a second comparison result by comparing the first to third voltages. The logic signal generator generates a first buffer output signal and a second buffer output signal, respectively, by transforming the first and second comparison results into logic signals based on internal voltage levels of a chip.
To further achieve the above objects in a whole or in part, a bonding option circuit according to the present invention is provided that includes a multi-level buffer that includes a first current control circuit coupled between a first node coupled to a pad and a first prescribed reference voltage, wherein a first current flows through the first current control circuit to the first node when a first control signal is not activated, and wherein a second current larger than the first current flows when the first control signal is activated, a resistor coupled between the first node and a second node, wherein a voltage difference is generated between the first and second nodes, a second current control circuit coupled between the second node and a second prescribed reference voltage, wherein a third current substantially equal to the first current flows through the second current control circuit when the first control signal is not activated, and wherein a fourth current substantially equal to the second current flows when the first control signal is activated, and a logic signal generator that generates a first buffer output signal and a second buffer output signal, respectively, by transforming signals of the first and second nodes into logic signals of prescribed internal voltage levels, and a decoder that activates one of a plurality of selection signals by decoding the first and second buffer output signals from the multi-level buffer.
To further achieve the above objects in a whole or in part, a bonding option circuit according to the present invention is provided that includes a variable voltage divider coupled to a pad that generates a first voltage, a second voltage, and a third voltage of which voltage levels are changed in accordance with conditions applied to a pad, wherein the variable voltage divider is activated by a first control signal, a comparator circuit that generates a first comparison result and a second comparison result by comparing the first to third voltages when activated by the first control signal, and a logic signal generator that generates a first buffer output signal and a second buffer output signal, respectively, by transforming the first and second comparison results into logic signals of prescribed internal voltage levels, and a decoder that activates one of a plurality of selection signals by decoding the first and second buffer output signals from the multi-level buffer.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.